Sensor to Image’s MIPI CSI-2 Receiver IP core provides a solution for decoding video streams from CSI-2 sensors in a Xilinx FPGA.
MIPI CSI-2 is one of the most widely used camera sensor interfaces with many applications requiring the connection to an FPGA for advanced image pre-processing and further transfer to a host system.
In order to shorten the development time, the IP core is delivered with a fully working reference design including Sensor to Image’s MVDK and an IMX274 MIPI FMC module
IPI CSI-2 Receiver IP Core
AT A GLANCE
- MIPI CSI-2 receiver and decoding block
- Configurable number of MIPI Lanes
- Using Xilinx D-PHY IP
- Delivered with a reference design for fast development
More info about Euresys and Sensor to Image please visit: https://www.euresys.com/Homepage
More info about Sales and Support contacts please visit: https://www.euresys.com/About-us/Contact-us